The present invention relates to a radio receiver and, more particularly, to a digital radio receiver which phase shifts its regenerated clock when an abnormal receiving condition is detected.
In general, an equalizer, for example a transversal filter, is used before or after signal detection in order to reduce distortion which occurs due to fading in radio communication. In this case, the parameters of the equalizer (for example, the tap coefficients of the transversal filter), are controlled on the basis of a signal condition before or after the equalization. If the distortion in the received signal exceeds the capability of the equalizer, an abnormal condition occurs, so that the error rate of discriminated data is deteriorated, and the carrier or clock cannot be regenerated. As a result, synchronization of the discrimination or equalization is destroyed. Under this condition, the parameters of the equalizer are altered and the correct values can no longer be recovered even after the distortion in the received signal is reduced so that it returns to a level at which equalization can take place normally. Therefore, in the prior art, when this type of abnormal condition is detected, the parameters of the equalizer are reset and are controlled again when the receiving condition has been recovered and the clock has been regenerated.
FIG. 1 is a block diagram of a part of a prior art radio receiver. A signal which is received and converted to the intermediate frequency is input to an input terminal 1. The intermediate frequency signal is converted, in a detector 2, to a baseband frequency signal by a recovered carrier sent from a carrier recovery circuit 6, equalized in an equalizer 3, and discriminated in a discriminator 4 to the nearest level from among plural reference levels. Finally, the signal is output to an output terminal 5 as output data.
The parameters of the equalizer 3 (for example, the tap coefficients of a transversal filter) are controlled by the discrimination result of the discriminator 4. A clock regeneration circuit 7 regenerates the clock from the intermediate frequency signal and sends it to discriminator 4, an abnormal receiving condition detection circuit 8, equalizer 3 and carrier recovery circuit 6.
The abnormal receiving condition detection circuit 8 monitors an error rate from the output of the discriminator 4, and resets the parameters of equalizer 3 when it determines that the receiving condition is abnormal. After the parameters are reset, equalizer 3 stops its operation.
As explained above, in the prior art, the parameters of the equalizer are reset when an abnormal receiving condition is detected and, therefore, a data signal cannot be received normally until synchronization is obtained under the nonequalized condition. As a result, the line application rate (i.e., the number of users per unit time) is deteriorated and the system has a greater amount of down time.